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Single-chip Type with built-in FET Switching Regulator Series
Output 0.5A or Less High Efficiency Step-down Switching Regulator with Built-in Power MOSFET
BD9122GUL
No.09027EAT31
Description ROHM's high efficiency step-down switching regulator (BD9122GUL) is a power supply designed to produce a low voltage including 1 volts from 5/3.3 volts power supply line. Offers high efficiency with our original pulse skip control technology and synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load. Features 1) Offers fast transient response with current mode PWM control system. TM 2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET) and SLLM (Simple Light Load Mode) 3) Incorporates soft-start function. 4) Incorporates thermal protection and ULVO functions. 5) Incorporates short-current protection circuit with time delay function. 6) Incorporates shutdown function 7) Employs WL-CSP : VCSP50L2 Use Power supply for LSI including DSP, Micro computer and ASIC Absolute Maximum Ratings (Ta=25) Parameter VCC Voltage PVCC Voltage EN Voltage SW,ITH Voltage Power Dissipation Operating temperature range Storage temperature range Maximum junction temperature
1 2
Symbol VCC PVCC VEN VSW,VITH Pd Topr Tstg Tjmax
Limits -0.3+7 1 -0.3+7 1 -0.3+7 -0.3+7 6602 -25+85 -55+150 +150
Unit V V V V mW
Pd should not be exceeded. Derating in done 5.28mW/ for temperatures above Ta=25, Mounted on 50mmx58mmx1.6mm Glass Epoxy PCB.
Operating Conditions (Ta=25) Parameter VCC Voltage PVCC Voltage EN Voltage SW average output Output voltage Setting Range
3 4
Symbol VCC *3 PVCC *3 EN Isw *3 VOUT
Min. 2.5*4 2.5*4 0 1.0
Limits Typ. 3.3 3.3 -
Max. 5.5 5.5 VCC 0.3 2.0
Unit V V V A V
Pd should not be exceeded. In case set output voltage 1.8V or more, VccMin = 2.7V.
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1/13
2009.05 - Rev.A
BD9122GUL
Electrical Characteristics (Ta=25, VCC=PVCC=3.3V, EN=VCC, R1=20k, R2=10k, unless otherwise specified.) Limits Parameter Symbol Min. Typ. Max. Standby current Bias current EN Low voltage EN High voltage EN input current Oscillation frequency Pch FET ON resistance Nch FET ON resistance ADJ Voltage Output voltage ITH SInk current ITH Source Current UVLO threshold voltage UVLO release voltage Soft start time Timer latch time Output Short circuit Threshold Voltage ISTB ICC VENL VENH IEN FOSC RONP RONN VADJ VOUT ITHSI ITHSO VUVLO1 VUVLO2 TSS TLATCH VSCP 2.0 0.8 0.780 10 10 2.2 2.22 0.5 1 0 250 GND VCC 1 1 0.3 0.2 0.800 1.200 20 20 2.3 2.35 1 2 VOUTx0.5 10 400 0.8 10 1.2 0.6 0.5 0.820 2.4 2.5 2 4 -
Technical Note
Unit A A V V A MHz V V A A V V ms ms V
Conditions EN=GND Standby mode Active mode VEN=3.3V PVCC=3.3V PVCC=3.3V
VADJ=1.0V VADJ=0.6V VCC=30V VCC=03V SCP/TSD operated VOUT=20V
Block Diagram, Application Circuit
VCC EN VREF PVCC Current Comp + RQ S Gm Amp SLOPE CLK OSC + VCC Soft Start UVLO TSD SCP ADJ ITH RITH CITH R1 R2 PGND GND Current Sense/ Protect + Driver Logic VCC 3.3V Input 10F
4.7H SW 4.7F
Output
Fig.1 Block Diagram
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2/13
2009.05 - Rev.A
BD9122GUL
Pin configuration
Technical Note
9122
Lot No.
SW B1
A1 PGND
(unit : mm)
PVcc B2 A2 GND
Vcc B3
A3 EN
ADJ B4
A4 ITH
TOP View
Fig.2 TOP View Pin number and function Pin No. Pin name A1 A2 A3 A4 B1 B2 B3 B4 PGND GND EN ITH SW PVCC VCC ADJ Nch FET source pin Ground Enable pinActive High
Fig.3 Physical Dimension : VCSP50L2
Pin function
Gm Amp output pin/Connected phase compensation capacitor Pch/Nch FET drain output pin Pch FET source pin Vcc power supply input pin Output voltage detect pin
Characteristics data(Reference data)
2.0
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
1.5
VOUT=1.5V Ta=25 Io=0A
2.0
2.0
VOUT=1.5V
1.5
1.5
VOUT=1.5V
1.0
1.0
1.0
0.5
0.5
VCC=3.3V Ta=25 Io=0A
0 1 2 3 EN VOLTAGE:VEN[V] 4 5
0.5
VCC=3.3V Ta=25
0.0 0 1 2 OUTPUT CURRENT:IOUT [A] 3
0.0 0 1 2 3 4 INPUT VOLTAGE:VCC[V] 5
0.0
Fig.4 Vcc - VOUT
Fig.5 VEN - VOUT
Fig.6 IOUT - VOUT
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3/13
2009.05 - Rev.A
BD9122GUL
Characteristics data(Reference data) - Continued
1.55 1.54
OUTPUT VOLTAGE:VOUT[V]
Technical Note
100
1.53 1.52 1.51 1.50 1.49 1.48 1.47 1.46 1.45
EFFICIENCY:[%]
70 60 50 40 30 20 10 0
FREQUENCY:FOSC[MHz]
VOUT=1.5V VCC=3.3V Io=0A
90 80
VOUT=1.5V
1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80
VCC=3.3V
VCC=3.3V Ta=25
1 10 100 OUTPUT CURRENT:IOUT[mA] 1000
-25 -15
-5
5
15
25
35
45
55
65
75
85
-25 -15
-5
5
15
25 35
45
55
65
75
85
TEMPERATURE:Ta[]
TEMPERATURE:Ta[]
Fig. 7 Ta - VOUT
0.35 0.30
ON RESISTANCE:R ON [ ]
Fig.8 Efficiency
2.0
400 370 CIRCUIT CURRENT:I CC [A] 340 310 280 250 220 190 160 130 100
-25 -15 -5 5 15 25 35 45 55 65 75 85
-25 -15
Fig.9 Ta - Fosc
VCC=3.3V
1.8 1.6
EN VOLTAGE:VEN[V]
VCC=3.3V
VCC=3.3V
0.25 0.20
1.4 1.2 1.0 0.8 0.6 0.4 0.2
PMOS
0.15
NMOS
0.10 0.05 0.00
-25 -15 -5 5 15 25 35 45 55 65 75 85
0.0
TEMPERATURE:Ta []
-5
5
15
25
35
45
55
65
75
85
TEMPERATURE:Ta[]
TEMPERATURE:Ta[]
Fig.10 Ta - RONN, RONP
1.2
Fig.11 Ta - VEN
Fig.12 Ta - Icc
Ta=25
FREQUENCY:FOSC[MHz] 1.1
VOUT=1.5V VCC=PVCC =EN SW
SLLMTM control
VOUT=1.5V
1
VOUT
0.9
VOUT VCC=3.3V Ta=25 Io=0A VCC=3.3V Ta=25
0.8 2.5
4 INPUT VOLTAGE:VCC[V]
5.5
Fig.13 Vcc - Fosc
PWM control VOUT=1.5V
Fig.14 Soft start waveform
Fig.15 SW waveform Io=10mA
VOUT=1.8V VOUT VOUT
VOUT=1.8V
SW
VOUT
VCC=3.3V Ta=25
IOUT
IOUT VCC=3.3V Ta=25 VCC=3.3V Ta=25
Fig.16 SW waveform Io=200mA
Fig.17 Transient Response Io=50125mA(10s)
Fig.18 Transient Response o=12550mA(10s)
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4/13
2009.05 - Rev.A
BD9122GUL
Information on advantages Advantage 1Offers fast transient response with current mode control system. BD9122GUL(transient response IO=50mA125mA)
VOUT=1.8V VOUT VOUT
Technical Note
VOUT=1.8V
IOUT
IOUT VCC=3.3V Ta=25 VCC=3.3V Ta=25
Io=50125mA Fig.19 Comparison of transient response Advantage 2 Offers high efficiency for all load range.
Io=12550mA
For lighter load: Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load.
Efficiency [%]
100
SLLMTM
For heavier load: Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor. ON resistance of P-channel MOS FET : 0.3(Typ.) ON resistance of N-channel MOS FET : 0.2(Typ.)
50
PWM
inprovement by SLLM system improvement by synchronous rectifier
0 0.001
0.01 0.1 Output current Io[A]
1
Fig.20 Efficiency Achieves efficiency improvement for heavier load. Offers high efficiency for all load range with the improvements mentioned above. Advantage 3Supplied in smaller package due to small-sized power MOS FET incorporated. Output capacitor Co required for current mode control: 10F ceramic capacitor Inductance L required for the operating frequency of 1 MHz: 2.2H inductor Reduces a mounting area required.
VCC 8mm RITH DC/DC Convertor Controller L VOUT Co 8mm CITH CVCC
Cin
RITH CITH
CIN CO
L
Fig.21 Example application
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5/13
2009.05 - Rev.A
BD9122GUL
Technical Note
Operation BD9122GUL is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load, while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency. Synchronous rectifier It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power dissipation of the set is reduced. Current mode PWM control Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback. PWM (Pulse Width Modulation) control The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P-channel MOS FET (while a N-channel MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation. SLLM (Simple Light Load Mode) control When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching dissipation and improves the efficiency.
SENSE Current Comp RESET Level Shift Gm Amp. ITH OSC RQ FB SET S Driver Logic SW Load IL VOUT
VOUT
Fig.22 Diagram of current mode PWM control
PVCC SENSE FB SET GND GND GND IL(AVE) SET PVCC SENSE FB GND GND
Current Comp
Current Comp
RESET SW IL
RESET SW
GND IL 0A
VOUT
VOUT(AVE)
VOUT
VOUT(AVE)
Not switching
Fig.23 PWM switching timing chart
Fig.24 SLLM
TM
switching timing chart
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6/13
2009.05 - Rev.A
BD9122GUL
Technical Note
Description of operations Soft-start function EN terminal shifted to "High" activates a soft-starter to gradually establish the output voltage with the current limited during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current. Shutdown function With EN terminal shifted to "Low", the device turns to Standby Mode, and all the function blocks including reference voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0F (Typ.). UVLO function Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of 50 mV (Typ.) is provided to prevent output chattering.
Hysteresis 50mV
VCC
EN
VOUT
Tss Soft start Standby mode Operating mode Standby mode UVLO
Tss
Tss
Operating mode
Standby mode EN
Operating mode
Standby mode
UVLO
UVLO
Fig.25 Soft start, Shutdown, UVLO timing chart Short-current protection circuit with time delay function Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO.
EN Output OFF latch
Output Short circuit Threshold Voltage VOUT IL Limit IL
Standby mode
t1t2=TLATCH
Standby mode
Operating mode
EN
Timer latch
EN
Fig.26 Short-current protection circuit with time delay timing chart
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7/13
2009.05 - Rev.A
BD9122GUL
Switching regulator efficiency Efficiency may be expressed by the equation shown below: POUT POUT VOUTxIOUT = x100[%]= x100[%]= VinxIin Pin POUT+PD
Technical Note
x100[%]
Efficiency may be improved by reducing the switching regulator power dissipation factors PD as follows: Dissipation factors: 2 1) ON resistance dissipation of inductor and FETPD(I R) 2) Gate charge/discharge dissipationPD(Gate) 3) Switching dissipationPD(SW) 4) ESR dissipation of capacitorPD(ESR) 5) Operating current dissipation of ICPD(IC)
2 2 1)PD(I R)=IOUT x(RCOIL+RON) (RCOIL[]DC resistance of inductor, RON[]ON resistance of FET, IOUT[A]Output current.) 2)PD(Gate)=CgsxfxV (Cgs[F]Gate capacitance of FET, f[H]Switching frequency, V[V]Gate driving voltage of FET) Vin2xCRSSxIOUTxf 3)PD(SW)= (CRSS[F]Reverse transfer capacitance of FET, IDRIVE[A]Peak current of gate.) IDRIVE 2 4)PD(ESR)=IRMS xESR (IRMS[A]Ripple current of capacitor, ESR[]Equivalent series resistance.) 5)PD(IC)=VinxICC (ICC[A]Circuit current.)
Consideration on permissible dissipation and heat generation As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be carefully considered. For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered. Because the conduction losses are considered to play the leading role among other dissipation mentioned above including gate charge/discharge dissipation and switching dissipation.
1.0
VCSP50L2(2.50x1.10mm) ROHM standard 1 layer board Board size50mmx58mm j-a=189.4/W
0.8 0.66W Power dissipation:Pd [W] 0.6
P=IOUT2xRON RON=DxRONP+(1-D)RONN DON duty (=VOUT/VCC) RCOILDC resistance of coil RONPON resistance of P-channel MOS FET RONNON resistance of N-channel MOS FET IOUTOutput current
0.4
0.2 0 0 25 50 75 100 125 150 Ambient temperature:Ta []
Fig.27 Thermal derating curve (VCSP50L2) If VCC=3.3V, VOUT=1.5V, RONP=0.3, RONN=0.2 IOUT=0.3A, for example, D=VOUT/VCC=1.5/3.3=0.45 RON=0.45x0.3+(1-0.45)x0.2 =0.135+0.11 =0.245[] P=0.32x0.24522.1[mW] As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
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8/13
2009.05 - Rev.A
BD9122GUL
Selection of components externally connected 1. Selection of inductor (L)
IL IL
Technical Note
The inductance significantly depends on output ripple current. As seen in the equation (1), the ripple current decreases as the inductor and/or switching frequency increases. IL= (VCC-VOUT)xVOUT LxVCCxf [A](1)
VCC
IL VOUT L Co
Appropriate ripple current at output should be 30% more or less of the maximum output current. IL=0.3xIOUTmax. [A](2) (VCC-VOUT)xVOUT [H](3) L= ILxVCCxf (IL: Output ripple current, and f: Switching frequency)
Fig.28 Output ripple current * Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating. * Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency. 2. Selection of output capacitor (CO)
VCC
Output capacitor should be selected with the consideration on the stability region and the equivalent series resistance required to smooth ripple voltage. Output ripple voltage is determined by the equation (4)
VOUT
VOUT=ILxESR [V](4) (IL: Output ripple current, ESR: Equivalent series resistance of output capacitor) * Rating of the capacitor should be determined allowing sufficient margin against output voltage. Less ESR allows reduction in output ripple voltage.
L
ESR Co
Fig.29 Output capacitor As the output rise time must be designed to fall within the soft-start time, the capacitance of output capacitor should be determined with consideration on the requirements of equation (5): Tss: Soft-start time TSSx(Ilimit-IOUT) Co (5) Ilimit: Over current detection level, 1A(Typ) VOUT if VOUT=1.5V, IOUT=0.3A, and TSS=1ms, 1mx(1-0.3) Co 467 [F] 1.5 Inappropriate capacitance may cause problem in startup. 10F to 100F ceramic capacitor is recommended. 3. Selection of input capacitor (Cin)
VCC
Cin
Input capacitor to select must be a low ESR capacitor of the capacitance sufficient to cope with high ripple current to prevent high transient voltage. The ripple current IRMS is given by the equation (6):
VOUT
L
Co
VCC < Worst case > IRMS(max.) When Vcc is twice the VOUT, IRMS=
IRMS=IOUTx
VOUT(VCC-VOUT)
[A](6) IOUT
Fig.30 Input capacitor
2 If VCC=3.3V, VOUT=1.5V, and IOUTmax.=0.3A IRMS=0.3x 1.5(3.3-1.5)
=0.15[ARMS] 3.3 A low ESR 10F/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
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9/13
2009.05 - Rev.A
BD9122GUL
Technical Note
4. Determination of RITH, CITH that works as a phase compensator As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.) A Gain [dB] fp(Max.) 0 IOUTMin. 0 IOUTMax. fz(ESR)
1 2xROxCO 1 fz(ESR)= 2xESRxCO fp= Pole at power amplifier When the output current decreases, the load resistance Ro increases and the pole frequency lowers. fp(Min.)= 1 2xROMax.xCO 1 2xROMin.xCO [Hz]with lighter load
Phase [deg]
-90
Fig.31 Open loop gain characteristics fp(Max.)= [Hz] with heavier load
A Gain [dB] 0 0 -90
fz(Amp.)
Zero at power amplifier Increasing capacitance of the output capacitor lowers the pole frequency while the zero frequency does not change. (This is because when the capacitance is doubled, the capacitor ESR reduces to half.) fz(Amp.)= 1 2xRITHxCITH
Phase [deg]
Fig.32 Error amp phase compensation characteristics
VCC
Cin EN VOUT VOUT ITH RITH CITH
VCC,PVCC
L SW ESR RO VOUT
GND,PGND
CO
Fig.33 Typical application Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance with CR zero correction by the error amplifier. fz(Amp.)= fp(Min.) 1 2xRITHxCITH = 1 2xROMax.xCO
5. Determination of output voltage The output voltage VOUT is determined by the equation (7): VOUT=(R2/R1+1)xVADJ(7) VADJ: Voltage at ADJ terminal (0.8V Typ.) With R1 and R2 adjusted, the output voltage may be determined as required.
L Output SW Co R2
Adjustable output voltage range : 1.0V2.0V Use 1 k100 k resistor for R1. If a resistor of the resistance higher than 100 k is used, check the assembled set carefully for ripple voltage etc.
ADJ
R1
Fig.34 Deter mination of output voltage
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10/13
2009.05 - Rev.A
BD9122GUL
Cautions on PC Board layout CO VOUT VCC R2 CIN L SW PVcc Vcc ADJ R1 Fig.35 Layout diagram PGND GND EN ITH CITH RITH
Technical Note
GND
EN
For the sections drawn with heavy line, use thick conductor pattern as short as possible. Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin PGND. Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.
Recommended components Lists on above application Symbol Part Value L Coil 2.2uH CIN Ceramic capacitor 10uF CO Ceramic capacitor 10uF VOUT=1.0V VOUT=1.2V CITH Ceramic capacitor VOUT=1.5V VOUT=1.8V VOUT=2.0V VOUT=1.0V VOUT=1.2V RITH Resistance VOUT=1.5V VOUT=1.8V VOUT=2.0V
Manufacturer FDK murata murata 2200pF murata 1000pF 6.8k ROHM 4.7k
Series MIPF2016D2R2 GRM188B30J106ME47B GRM188B30J106ME47B
GRM15 Series
MCR006 6801 MCR006 4701
* The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode established between the SW and PGND pins.
I/O equivalent circuit
EN pin SW pin
PVCC PVCC PVCC
EN SW
ITH pin
VCC
ADJ pin
ADJ ITH
Fig.36 I/O equivalent circuit
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11/13
2009.05 - Rev.A
BD9122GUL
Technical Note
Cautions on use 1. Absolute Maximum Ratings While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses. 2. Electrical potential at GND GND must be designed to have the lowest electrical potential In any operating conditions. 3. Short-circuiting between terminals, and mismounting When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and power supply or GND may also cause breakdown. 4.Operation in Strong electromagnetic field Be noted that using the IC in the strong electromagnetic radiation can cause operation failures. 5. Thermal shutdown protection circuit Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be used thereafter for any operation originally intended. 6. Inspection with the IC set to a pc board If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the inspection process, be sure to turn OFF the power supply before it is connected and removed. 7. Input to IC terminals + This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the N-layer of each element form a P-N junction, and various parasitic element are formed. If a resistor is joined to a transistor terminal as shown in Fig 37. P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and if GND>Terminal B (at NPN transistor side), a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode. The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements.
Resistor Pin A Pin A
P
+
Transistor (NPN) Pin B
C B E B P P
+
Pin B
N P P
+
N
N
Parasitic element
N
P+
N N
C E
P substrate Parasitic element
GND
P substrate Parasitic element
GND GND GND
Parasitic element
Other adjacent elements
Fig.37 Simplified structure of monorisic IC 8. Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
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12/13
2009.05 - Rev.A
BD9122GUL
Ordering part number
Technical Note
B
D
9
Part No. 9122
1
2
2
G
U
L
-
E
2
Part No.
Package GUL: VCSP50L2
Packaging and forming specification E2: Embossed tape and reel (VCSP50L2)
VCSP50L2

Tape Quantity Direction of feed Embossed carrier tape 3000pcs E2
(The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand.)
1234
1234
1234
1234
1234
1234
(Unit:mm)
Reel
1Pin
Direction of feed
When you order , please order in times the amount of package quantity.
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13/13
2009.05 - Rev.A
Notice
Notes
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